(1) Field of the Invention
This inventions relates to a method of fabrication used in the semiconductor integrated circuit devices, and more specifically to the formation of planarized structures of conducting copper lines and interconnects using the CMP (Chemical Mechanical Polish) dual damascene technique with a unique double CMP barrier layer.
(2) Description of Related Art
In the fabrication of semiconductor integrated circuits CMP (Chemical Mechanical Polish) is used to remove conducting metal in a dual damascene process. Conducting metal is inlaid into trench and via structures of insulating material. The trenches and vias are usually filled with copper and the insulating material is typically insulating oxide defined by photo lithography.
The CMP process polishes back the excess copper and any surrounding material at the same time. Key to the process is the polishing rate of copper and the surrounding material. The softer copper metal typically polishes back at a faster rate than the surrounding material causing dishing in the copper structures. This lack of planarity caused by different CMP polishing rates among different materials presents a challenge to the Semiconductor Industry. Ideally, the CMP polishing rate of copper and that of the surrounding material should be, such that copper is polished without any dishing, while also removing the barrier layers, and stopping on insulating layer without removing the insulating layer.
U.S. Pat. No. 5,736,192 entitled "Embedded Electroconductive Layer and Method for Formation Thereof" granted Apr. 7, 1998 to Shigeru Okamoto describes a method of forming a copper interconnect using a TiN layer to aid in the CVD deposition of copper. A diffusion barrier layer for copper is listed as a TaN or WN layer. The embedded copper is patterned by a damascene CMP process.
U.S. Pat. No. 5,731,245 entitled "High Aspect Ratio Low Resistivity Lines/Vias with Tungsten-Germanium Alloy Hard Cap" granted Mar. 24, 1998 to Rajiv Vassant Joshl, et al, shows a CMP process for a copper layer using a hard CMP stopping layer. The invent teaches that copper or Al-Cu layer, in a trench or via fill process, is capped by a refractory metal. A layer of W-Ge is deposited over the refractory material layer and metallization. The hard, wear-resistant W-Ge layer acts as a polishing stop, in alumina slurry or ferric nitrate CMP.
U.S. Pat. No. 5,676,587 entitled "Selective Polish Process For Titanium, Titanium Nitride, Tantalum and Tantalum Nitride" granted Oct. 14, 1997 to William Francis Landers, et al, describes CMP method whereby W or Cu is removed by a two-step CMP process from an oxide layer. The damascene method uses an underlying Ti/TiN or Ta/TaN via liner layer, which protects the underlying oxide layer. This underlying layer is selectively removed in step two, of the two-step CMP process, by utilizing a neutral pH silica based slurry.
U.S Pat. No. 5,739,579 entitled "Method for Forming Interconnections for Semiconductor Fabrication and Semi-Conductor Device Having Such Interconnections" granted Apr. 14, 1998 to Chien Chiang and David B. Fraser describes multilayer interconnects (plugs) and conducting lines formed by CMP. Copper metal is surrounded by diffusion barrier layer of titanium nitride and silicon oxynitride. Silicon nitride is used as a key etch stop on top oxide for CMP process.
U.S. Pat. No. 5,705,430 granted Jan. 6, 1998 to Steven Avanzino, et al, teaches a method of improving a dual CMP damacene process by forming the conductive lines and conductive vias with two etch steps of an insulating layer that produces sharply defined edges of the via openings.
U.S. Pat. No. 5,677,244 to Venkatraman describes a dual damascene structure that utilizes a copper diffusion barrier layer and seed layer combined. CVD copper is used for the conducting lines and vias and removed by CMP. Barrier layer material lists Ti, TiN, Cu and Al.
U.S. Pat. No. 5,723,387 to Chen describes a method and apparatus for forming Cu interconnect metallurgy on semiconductor substrates. A self contained unit for forming Cu metallurgy interconnection structures is described, which reduces the number of times wafers are transferred between wet process stations.